A general mathematical model of probabilistic ripple-carry adders

Author

Lau, Mark S K ; Ling, Keck-voon ; Chu, Yun-Chung ; Bhanu, Arun

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2010

fDate

8-12 March 2010

Firstpage

1100

Lastpage

1105

Abstract

Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible to trade correctness of circuit operations for potentially significant energy saving. For systematic design of probabilistic circuits, accurate mathematical models are indispensable. To this end, we propose a model of probabilistic ripple-carry adders. Compared to existing models, ours is applicable under a wide range of noise assumptions, including the popular additive-noise assumption. Our model provides recursive equations that can accurately capture propagation of carry errors. The proposed model is validated by HSPICE simulation, and we find that the model is able to predict multi-bit error-rates of a simulated probabilistic ripple-carry adder with reasonable accuracy.

Keywords

CMOS integrated circuits; SPICE; adders; carry logic; circuit simulation; error statistics; integrated circuit design; probability; HSPICE simulation; additive-noise assumption; carry error propagation; energy saving; mathematical model; multibit error-rate; probabilistic CMOS technology; probabilistic circuit design; probabilistic ripple-carry adder; recursive equation; systematic design; Adders; Birth disorders; CMOS technology; Equations; Error probability; Logic circuits; Logic gates; Mathematical model; Power engineering and energy; Predictive models;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4244-7054-9

Type

conf

DOI

10.1109/DATE.2010.5456973

Filename

5456973