A new low-voltage charge pump circuit for PLL

Author

Chang, Robert C. ; Kuo, Lung-Chih

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

Volume

5

fYear

2000

fDate

2000

Firstpage

701

Abstract

In this paper, a new low-voltage charge pump circuit is presented. Its simple and symmetric structure can provide more stable operation. The proposed charge pump circuit is composed of a pair of symmetric pump circuits and a wide-swing current mirror circuit. To ensure more accurate charge pumping operation, a weak pull-up circuit is inserted in the symmetric pump circuit. The new charge pump circuit has wide output range and no jump phenomenon. It has been designed by using the MOSIS 0.35 μm double-poly triple-metal CMOS technology and simulated by HSPICE. The power consumption of the proposed charge pump circuit is 0.03 mW at a supply voltage of 1.5 V. The circuit can be widely used in either single-ended or fully differential phase-locked loop structures

Keywords

CMOS integrated circuits; SPICE; circuit simulation; current mirrors; low-power electronics; phase locked loops; 0.03 mW; 0.35 micron; 1.5 V; HSPICE; MOSIS; PLL; double-poly triple-metal CMOS; fully differential phase-locked loop structures; low-voltage charge pump circuit; output range; power consumption; symmetric structure; weak pull-up circuit; wide-swing current mirror circuit; CMOS technology; Charge pumps; Circuits; Operational amplifiers; Phase frequency detector; Phase locked loops; Switches; Virtual colonoscopy; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857586

Filename

857586