23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration

Author

Oshima, Takashi ; Takahashi, Tomomi ; Yamawaki, Taizo

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

2009

fDate

24-27 May 2009

Firstpage

960

Lastpage

963

Abstract

A novel nonlinear foreground calibration of pipeline A/D converters based on LMS algorithm has been proposed and verified by macro-based simulation as well as measurement of test chip. The prototype 23-mW 50-MS/s 10-bit pipeline ADC in 0.13-mum CMOS has confirmed that the proposed calibration can accurately and rapidly correct the inaccuracy caused both by heavy nonlinearity of low-gain op-amps and by their incomplete settling without requiring any dedicated voltage references, complicated structures or timing sequence and hence can be used for various applications.

Keywords

CMOS integrated circuits; analogue-digital conversion; least mean squares methods; CMOS; macrobased simulation; nonlinear LMS foreground calibration; op-amps; pipeline AD converter; power 23 mW; size 0.13 micron; word length 10 bit; Calibration; Circuits; Error correction; Least squares approximation; Operational amplifiers; Pipelines; Polynomials; RF signals; Timing; Voltage; LMS algorithm; Pipeline ADC; foreground calibration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5117917

Filename

5117917