Title :
A time-interleaved flash-SAR architecture for high speed A/D conversion
Author :
Sung, Ba Ro Saim ; Cho, Sang-Hyun ; Lee, Chang-Kyo ; Kim, Jong-In ; Ryu, Seung-Tak
Author_Institution :
Sch. of Eng., Inf. & Commun. Univ., Daejeon, South Korea
Abstract :
A time-interleaved flash-SAR ADC architecture has been suggested for high speed A/D conversion. Owing to the MSBs determined by the front end flash ADC, SAR ADC completes the A/D conversion in a reduced number of cycles. Time-interleaved SAR ADCs with a commonly shared low resolution flash ADC provide a new size and power efficient high speed ADC architecture. The proposed ADC structure has been verified by developing a behavioral model of a 6-bit 1.2 GHS/s ADC. Circuit design considerations have also been discussed based on the sampling network mismatch between the flash and SAR ADCs.
Keywords :
analogue-digital conversion; low-power electronics; analog to digital conversion; circuit design; high speed A/D conversion; low power successive approximation register; time-interleaved flash-SAR architecture; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Hardware; High speed optical techniques; Magnetic memory; Optical receivers; Sampling methods; Timing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117923
