Title :
Carbon nanotube circuits: Living with imperfections and variations
Author :
Zhang, Jie ; Patil, Nishant ; Lin, Albert ; Wong, H. S Philip ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon CMOS. However, CNFET circuits are subject to several sources of imperfections. These imperfections lead to incorrect logic functionality and substantial circuit performance variations. Processing techniques alone are inadequate to overcome the challenges resulting from these imperfections. An imperfection-immune design methodology is required. We present an overview of imperfection-immune design techniques to overcome two major sources of CNFET imperfections: metallic Carbon Nanotubes (CNTs) and CNT density variations.
Keywords :
carbon nanotubes; field effect transistor circuits; integrated circuit design; CNFET circuits; CNT density variations; carbon nanotube circuits; carbon nanotube field-effect transistors; circuit performance variations; energy-delay-product; imperfection-immune design; logic functionality; metallic carbon nanotubes; silicon CMOS; CMOS logic circuits; CMOS technology; CNTFETs; Carbon nanotubes; Circuit optimization; Computer science; Logic circuits; Semiconductivity; Silicon; Substrates;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5456983