A digitally trimmable low-noise low-power analog front-end for EEG signal acquisition

This paper presents a digitally trimmable low-noise low-power amplifier for EEG signal acquisition. The gain is 3-bit programmable from 54.2dB to 72.3dB and the high cutoff frequency can be adjusted using 3 bits from 152Hz to 360Hz. A T-network capacitor structure is proposed to reduce the capacitor area on chip. By increasing the size of the input transistors and operating MOS transistors in the subthreshold region, low noise and low power consumption can be achieved. Simulation shows the input referred noise of the system is 2.2 μVrms from 0.1Hz to 360Hz, and the current consumption of the amplifier is 700nA at 1.8V supply, and the NEF is 3.54. The amplifier is under fabrication using a TSMC 0.18μm 1P6M CMOS process. It has been shown that this low-noise, low-power amplifier is suitable for a portable EEG acquisition device.