• DocumentCode
    2255052
  • Title

    Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor

  • Author

    Amano, Hideharu ; Kimura, Masayuki ; Ozaki, Nobuaki

  • Author_Institution
    Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
  • fYear
    2012
  • fDate
    20-22 Sept. 2012
  • Firstpage
    92
  • Lastpage
    99
  • Abstract
    Although context memory or configuration cache is a key mechanism for quick dynamic reconfiguration of multi-context Dynamically Reconfigurable Processing Array (DRPA), it requires a large amount of area and energy. In order to save them, methods to remove the context memory from multi-context DRPA are proposed. In order to keep a context without switching, Loop Separation for Keeping Datapath (LSKD)is introduced. By separating loops by the compiler and some additional hardware, the same context can be used without switching in a certain clock cycles. The back-ground configuration data loading time can be reduced by multicasting configuration data with two dimensional bit-map. For further reduction, the differential loading and spare register are proposed. With combination of them, the increasing execution time is only up to 12-13% if the target application does not have loop-carried dependency. With the above overhead on the performance, the semiconductor area becomes 63%, and the energy consumption is reduced to 40%, thus, the performance per cost or energy is much improved.
  • Keywords
    cache storage; program compilers; program control structures; reconfigurable architectures; DRPA; LSKD; back-ground configuration data loading time; compiler; configuration cache; context memory removal; differential loading; energy consumption; loop separation for keeping datapath; loops; multicasting configuration data; multicontext dynamically reconfigurable processing array; multicontext dynamically reconfigurable processor; semiconductor area; spare register; two dimensional bit-map; Clocks; Context; Hardware; Loading; Memory management; Registers; Switches; Dynamically Reconfigurable Processors; Multi-context memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on
  • Conference_Location
    Aizu-Wakamatsu
  • Print_ISBN
    978-1-4673-2535-6
  • Electronic_ISBN
    978-0-7695-4800-5
  • Type

    conf

  • DOI
    10.1109/MCSoC.2012.35
  • Filename
    6354683