A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs

Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new FPGA devices very advantageous for space and avionics computing. However, larger levels of integration makes FPGA´s configuration memory more prone to suffer Multi-Cell Upset errors (MCUs), caused by a single radiation particle that can flip the content of multiple nearby cells. In particular, MCUs are on the rise for the new generation of SRAM-based FPGAs, since their configuration memory is based on volatile programming cells designed with smaller geometries that result more sensitive to proton- and heavy ion-induced effects. MCUs drastically limits the capabilities of specific hardening techniques adopted in space-based electronic systems, mainly based on Triple Modular Redundancy (TMR). In this paper we describe a new placement algorithm for hardening TMR circuits mapped on SRAM-based FPGAs against the effects of MCUs. The algorithm is based on layout information of the FPGA´s configuration memory and on metrics related to the logic and interconnection resources locations. Experimental results obtained from MCU static analysis on a set of benchmark circuits hardened by the proposed algorithm prove the efficiency of our approach.