Title :
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
Author :
Wang, B.T. ; Kuo, James B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results
Keywords :
CMOS memory circuits; SPICE; SRAM chips; VLSI; cellular arrays; circuit simulation; low-power electronics; two-port networks; 1 V; SPICE results; low-voltage VLSI SRAM; single-bit-line simultaneous read-and-write access; source terminal; two-port 6T CMOS SRAM cell structure; write word line; Driver circuits; Joining processes; MOS devices; Power supplies; Random access memory; Read-write memory; SPICE; Threshold voltage; Very large scale integration; Virtual manufacturing;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857606
