Designing a low-power (self-timed) router for a MIMD computer

This paper describes the building of a self-timed cell-set for an asynchronous router. The efficiency of such a routing scheme has been fully demonstrated. The description of the circuit´s behavior in the form of communicating hardware processes leads to a modular representation of its architecture. Then specific cells are needed to actually implement those modules, both for control and data-path. This involves a full-custom design described in the present paper. Hazard-freeness relies on an original methodology respective to an accurate choice of delay models. Measured performances of the circuit and cells conclude the paper. Low power consumption is exhibited