Designing a low-power (self-timed) router for a MIMD computer

Author

Senn, Eric ; Zavidovique, Bertrand

Author_Institution

LESTER, South Britany Univ., Lorient, France

Volume

5

fYear

2000

fDate

2000

Firstpage

737

Abstract

This paper describes the building of a self-timed cell-set for an asynchronous router. The efficiency of such a routing scheme has been fully demonstrated. The description of the circuit´s behavior in the form of communicating hardware processes leads to a modular representation of its architecture. Then specific cells are needed to actually implement those modules, both for control and data-path. This involves a full-custom design described in the present paper. Hazard-freeness relies on an original methodology respective to an accurate choice of delay models. Measured performances of the circuit and cells conclude the paper. Low power consumption is exhibited

Keywords

VLSI; asynchronous circuits; circuit stability; delay estimation; integrated circuit layout; logic design; low-power electronics; network routing; parallel architectures; MIMD computer; asynchronous router design; communicating hardware processes; control path; data path; delay models; full-custom design; hazard-free design; low power consumption; low-power router; modular representation; self-timed cell-set; self-timed comparator; self-timed router; stability detection; Buildings; Circuits; Control systems; Delay; Energy consumption; Hardware; Parallel machines; Performance evaluation; Power system modeling; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857607

Filename

857607