Formal verification of analog circuits in the presence of noise and process variation

Author

Narayanan, Rajeev ; Akbarpour, Behzad ; Zaki, Mohamed H. ; Tahar, Sofiène ; Paulson, Lawrence C.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada

fYear

2010

fDate

8-12 March 2010

Firstpage

1309

Lastpage

1312

Abstract

We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose to use stochastic differential equations (SDE) to model the designs. We find a closed form solution for the SDEs, then integrate the device variation due to the 0.18??m fabrication process and verify properties using MetiTarski. We illustrate the proposed approach on an inverting Op-Amp Integrator and a Band-Gap reference bias circuit.

Keywords

analogue circuits; differential equations; formal verification; operational amplifiers; reference circuits; MetiTarski; analog circuits; analog designs; automated theorem prover; band-gap reference bias circuit; formal verification; inverting op-amp integrator; noise variation; process variation; size 0.18 mum; stochastic differential equations; Analog circuits; Analog computers; Circuit noise; Circuit simulation; Closed-form solution; Computational modeling; Formal verification; Mathematical model; Operational amplifiers; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4244-7054-9

Type

conf

DOI

10.1109/DATE.2010.5457009

Filename

5457009