DocumentCode
2255618
Title
Asynchronous switching for low-power Octagon network-on-chip
Author
El-Moursy, Magdy A. ; Shawkey, Heba A.
Author_Institution
Mentor Graphics Corp., Cairo, Egypt
fYear
2010
fDate
19-22 Dec. 2010
Firstpage
256
Lastpage
259
Abstract
Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports αd is less than A αc + B αclk. Closed form expressions for power dissipation of Octagon topology are provided for both synchronous and asynchronous switching. The area of the asynchronous switch is 50% greater than the area of the synchronous switch. However, the power dissipation of asynchronous switching could be decreased by up to 73.6%. Asynchronous switching becomes more efficient as technology advances and network density increases. A reduction in power dissipation reaches 81.3% for 256 IPs with the same chip size. Even with clock gating, asynchronous switching achieves significant power reduction of 76.7% for 75% clock activity factor.
Keywords
asynchronous circuits; clocks; low-power electronics; network topology; network-on-chip; IP; Octagon topology; asynchronous switching; chip size; clock activity factor; clock gating; data transfer; low-power Octagon network-on-chip; network density; power dissipation; power reduction; Clocks; Network topology; Power dissipation; Repeaters; Switches; Synchronization; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (ICM), 2010 International Conference on
Conference_Location
Cairo
Print_ISBN
978-1-61284-149-6
Type
conf
DOI
10.1109/ICM.2010.5696132
Filename
5696132
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