High-speed Inter-IC Interfacing for Mobile Multimedia Applications

Distributed processing in today´s mobile multimedia devices requires efficient ways of inter-IC communication. This paper presents a hardware block allowing the host IC to have parallel asynchronous access to the resources of the target IC. The block targets mobile multimedia applications. It is composed of an asynchronous logic subsystem, configuration registers, a packer, 4 command/data FIFOs, 3 packer FIFOs, 8 device transaction level (DTL) masters and a DTL slave. The block allows the target IC to be directly connected to a memory controller. The block supports 2D transfers, which improves performance and saves power for mobile video applications.