Leakage reduction in FPGA routing multiplexers

There is a pressing need to reduce the static power consumption in FPGAs implemented in deep submicron so that it can also be used in portable battery operated devices. The multiplexer based interconnect matrix of an FPGA consumes most of the static power consumption. This paper investigates reducing leakage power in unused FPGA routing multiplexers by controlling their inputs at the deep submicron 22 nm technology node. HSPICE simulation using Berkeley Predictive technology models (BPTM) on different sizes and topologies of routing multiplexers show that the minimum leakage vector at the 22 nm technology node significantly varies from that at 65 nm node. This is due to higher gate leakage and output stage loading effects. The application of this vector results in 20% more leakage power saving as compared to the existing approaches. This technique saves significant leakage power because most of the routing multiplexers are unused in an FPGA. Moreover, there is no area overhead contrary to the existing approaches.