DocumentCode :
2255899
Title :
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Author :
Yang, Fan ; Cai, Yici ; Zhou, Qiang ; Hu, Jiang
Author_Institution :
Dept. of CST, Tsinghua Univ., Beijing, China
fYear :
2010
fDate :
8-12 March 2010
Firstpage :
1369
Lastpage :
1372
Abstract :
Manufacturing hotspots are the layout patterns which cause excessive difficulties to manufacturing process. Design rules are effective at handling sizing/spacing induced hotspots, but are inadequate at dealing with topological hotspots. In wire routings, existing approaches often remove the hotspots through iteratively ripping up and rerouting one net at a time guided by litho-simulations. This procedure can be very time-consuming because litho-simulation is typically very slow and the rerouting may result in new hotspots due to its heuristic nature. In this paper, we propose a new approach for improving the efficiency of hotspot removal. In our approach, multiple nets in each hotspot region are simultaneously ripped up and rerouted based on Boolean satisfiability (SAT). The hotspot patterns, which are described and stored in a pre-built library, are forbidden to appear in the reroute through SAT constraints. Since multiple nets are simultaneously processed and SAT can guarantee to find a feasible solution if it exists, our approach can greatly accelerate the convergence on manufacturability. Experimental results on benchmark circuits show that our approach can remove over 90% of the hotspots in less than one minute on circuits with more than 20K nets and hundreds of hotspots.
Keywords :
Boolean algebra; circuit layout CAD; computability; design for manufacture; Boolean satisfiability; SAT based multi-net rip-up-and-reroute; SAT constraints; benchmark circuits; design rules; hotspot patterns; hotspot region; layout patterns; litho-simulations; manufacturability; manufacturing hotspot removal; topological hotspots; wire routings; Acceleration; Circuit simulation; Costs; Libraries; Lithography; Manufacturing processes; Process design; Routing; Runtime; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
ISSN :
1530-1591
Print_ISBN :
978-1-4244-7054-9
Type :
conf
DOI :
10.1109/DATE.2010.5457024
Filename :
5457024
Link To Document :
بازگشت