Title :
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector
Author :
Cupaiuolo, Teo ; Siti, Massimiliano ; Tomasoni, Alessandro
Author_Institution :
Adv. Syst. Technol., STMicrolectronics, Agrate Brianza, Italy
Abstract :
In this paper a VLSI architecture of a high throughput and high performance soft-output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. maximum-likelihood - ML - in the max-log sense) SO generation. A reduced complexity variant of the SO generation stage is also described. To the best of the authors´ knowledge, the proposed architecture is the first VLSI implementation of a max-log ML MIMO detector which includes QR decomposition and SO generation, having the latter a deterministic very high throughput thanks to a fully parallelizable structure, and parameterizability in terms of both the number of transmit and receive antennas, and the supported modulation orders. The two designs achieve a very high throughput making them particularly suitable for MIMO-OFDM systems like e.g. IEEE 802.11n WLANs: the most demanding requirements are satisfied at a reasonable cost of area and power consumption.
Keywords :
MIMO communication; OFDM modulation; VLSI; receiving antennas; signal detection; transmitting antennas; LORD; MIMO-OFDM system; layered orthogonal lattice detector; low complexity high throughput VLSI architecture; modulation order; receive antenna; soft output maximum likelihood MIMO detector; transmit antenna; Algorithm design and analysis; Detectors; Fading; Lattices; MIMO; OFDM; Receiving antennas; Throughput; Transmitting antennas; Very large scale integration;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5457031