Design and layout of Schottky diodes in a standard CMOS process

This paper addresses several concerns for increasing the frequency range in a Schottky diode detector circuit through a layout design solution. To increase the frequency and active range of the diode, reducing the series resistance was the first concern addressed, and this was accomplished by interdigitating the fingers of the Schottky and ohmic contacts. The capacitor was laid out in a manner to decrease charge lost to the substrate through parasitic substrate capacitance. For added accuracy, an averaging resistor/capacitor was added to isolate the Schottky diode detector circuit from the measuring circuit. With these improvements in the layout design, it is expected that the frequency and dynamic range of the Schottky diodes in the detector circuit will be extended further into the GHz range