Design of a 16-bit CMOS divider/square-root circuit

Author

Ren, Hongge ; Hoang, Loc B. ; Chen, Hsin-Chia ; Wei, Belle W Y

Author_Institution

Dept. of Electr. Eng., San Jose State Univ., CA, USA

fYear

1993

fDate

1-3 Nov 1993

Firstpage

807

Abstract

We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in digital signal applications. The circuit uses the nonrestoring method to obtain quotient (root) bits. The quotient (root) value in each iterative step is kept in binary form whereas the partial remainders (radicands) are in redundant binary representations. The iterative core is a redundant binary and binary subtraction, implemented by a carry-save adder. The quotient (root) bit selection logic inputs leading three digits of partial remainders (radicands) and can be implemented in a simple circuit. The resultant circuit in 1.2 μm CMOS technology has an area of 6.72 mm² and a speed of 47.7 ns and 49.2 ns for rounded quotient and square-root outputs respectively

Keywords

CMOS digital integrated circuits; VLSI; adders; digital arithmetic; digital signal processing chips; dividing circuits; iterative methods; redundant number systems; 1.2 micron; 16 bit; 47.7 ns; 49.2 ns; CMOS divider/square-root circuit; DSP chip; carry-save adder; digital signal applications; iterative core; nonrestoring method; partial remainders; radicands; redundant binary representations; Adders; CMOS logic circuits; CMOS technology; Digital arithmetic; Educational institutions; Iterative algorithms; Lab-on-a-chip; Logic circuits; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-4120-7

Type

conf

DOI

10.1109/ACSSC.1993.342633

Filename

342633