Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the context-based adaptive variable length coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for high definition (HD) (1920times1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.