Hardware-assisted syntax decoding model for software AVC/H.264 decoders

In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG reconfigurable video coding (RVC) Framework. A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2).