A novel SAR Fast-locking digital PLL: Behavioral modeling and simulations using VHDL-AMS

A novel successive-approximation fast-locking digital phase-locked loop (SAR DPLL) is presented and behaviorally modeled using VHDL-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a successive-approximation algorithm similar to the one employed in SAR A/D converters (ADCs) and (2) a fine-tuning stage for phase tracking which is similar to conventional DPLLs. The coarse-tuning stage includes a frequency comparator, a successive-approximation register, a D/A converter (DAC), and control logic. Design considerations and implementation are presented in this paper. VHDL-AMS and Ansoft Simplorer are used to design and perform simulations. The fast-locking DPLL saves about 50% of the lock time as compared to its conventional DPLL counterpart.