Hardware implementation of DES using pipelining concept with time-variable key

This paper describes two high-performance reconfigurable hardware implementations of the Data Encryption Standard (DES) algorithm. This is achieved by combining pipelining concept with time-variable key technique. The two proposed schemes change the key with time. The first one uses a counter to change the key every clock cycle. The second changes the key using a pseudorandom number generator. Using time-variable key technique enhances the security of DES because the same plaintext is ciphered to different cipher texts by time. Hackers will face difficulty to hack into the proposed schemes because of time-variant behavior. Final 16-stage pipelined design of the two proposed schemes is implemented on Xilinx Spartan-3e Field Programmable Gate Array (FPGA) technology. The 16-stage pipelined design of the first scheme is achieved with encryption rate of 7.97 Gbit/s and 2697 number of Configurable logic blocks (CLBs). The second operates at data rates up to 7.26 Gbit/s and 2566 CLBs. The two proposed hardware designs are more secure than any previous hardware design and among the fastest implementations with better area utilization.