Title :
Design techniques for high performance CMOS flash analog-to-digital converters
Author :
Park, Sunghyun ; Flynn, Michael P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fDate :
28 Aug.-2 Sept. 2005
Abstract :
This paper reviews the limitations in the performance of CMOS flash ADCs. Methods to enhance sampling rate, such as interleaving and latch cascading, are discussed, and a method that employs inductors to improve comparator performance is presented. We also consider the benefits and trade-offs of implementing a flash ADC without a track-and-hold.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); inductors; integrated circuit design; sample and hold circuits; CMOS flash analog-to-digital converters; inductors; interleaving technique; latch cascading; sampling rate enhancement; track-and-hold circuit; Analog-digital conversion; CMOS technology; Circuits; Equations; Inverters; Latches; Preamplifiers; Sampling methods; Signal resolution; Voltage;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1522927
