Decimal Floating Point for future processors

Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.