Throughput maximization for wave-pipelined interconnects using cascaded buffers and transistor sizing

This paper presents two new design methodologies for throughput-centric wave-pipelined interconnects: cascaded buffers insertion and transistor sizing. Experimental results show that up to 185% throughput improvement can be achieved by applying the new proposed approaches compared with conventional interconnect optimization techniques, such as buffer insertion. Moreover, with the combination of cascaded buffers insertion and adequate techniques in supply voltage scaling, up to 60% dynamic power reduction can be gained compared to the conventional design.