DocumentCode
2256734
Title
A loop optimization technique for speculative chip multiprocessors
Author
Wu, Chao-Chin ; Lai, Kuan-Chou
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., National Changhua Univ. of Educ.
fYear
0
fDate
0-0 0
Abstract
According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations
Keywords
microprocessor chips; multiprocessing systems; parallel programming; program control structures; dependence violations; loop optimization; speculative chip multiprocessor; system performance; Algorithms; Chaos; Computer science; Computer science education; Educational programs; System performance; Systems engineering education;
fLanguage
English
Publisher
ieee
Conference_Titel
Networking, Architecture, and Storages, 2006. IWNAS '06. International Workshop on
Conference_Location
Shenyang
Print_ISBN
0-7695-2651-9
Type
conf
DOI
10.1109/IWNAS.2006.9
Filename
1654530
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