Optimal regulation of traffic flows in networks-on-chip

We have proposed (??, ??)-based flow regulation to reduce delay and backlog bounds in SoC architectures, where ?? bounds the traffic burstiness and ?? the traffic rate. The regulation is conducted per-flow for its peak rate and traffic burstiness. In this paper, we optimize these regulation parameters in networks on chips where many flows may have conflicting regulation requirements. We formulate an optimization problem for minimizing total buffers under performance constraints. We solve the problem with the interior point method. Our case study results exhibit 48% reduction of total buffers and 16% reduction of total latency for the proposed problem. The optimization solution has low run-time complexity, enabling quick exploration of large design space.