An embedded wide-range and high-resolution CLOCK jitter measurement circuit

Author

Lee, Yu ; Yang, Ching-Yuan ; Cheng, Nai-Chen Daniel ; Chen, Ji-Jan

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2010

fDate

8-12 March 2010

Firstpage

1637

Lastpage

1640

Abstract

The paper describes an embedded circuit for the single shot jitter measurement of the clock signal. Based on a jitter amplified technique with a pulse removing mechanism, the pico-second level resolution is achieved in the wide frequency range. In addition, a gain-locked loop calibration scheme is proposed to keep the amplification ratio constant under PVT variations. Fabricated by 0.13-um CMOS process, the tested circuit can achieve a resolution of 2 ps root mean square (rms) jitter at an input range from few tens of megahertz to 1.6 GHz.

Keywords

CMOS integrated circuits; calibration; clocks; jitter; mean square error methods; time measurement; CMOS process; clock jitter measurement circuit; clock signal; embedded circuit; gain-locked loop calibration; pico-second level resolution; root mean square; single shot jitter measurement; size 0.13 mum; tested circuit; wide frequency range; Calibration; Circuit testing; Clocks; Design for testability; Frequency; Jitter; Paper technology; Pulse amplifiers; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4244-7054-9

Type

conf

DOI

10.1109/DATE.2010.5457074

Filename

5457074