CMOS SFFDS PA with coupled transformer for high power RF applications

Author

Luque, Y. ; Kerhervé, E. ; Deltimple, N. ; Belot, D.

Author_Institution

IMS Lab., Univ. of Bordeaux, Talence, France

fYear

2009

fDate

24-27 May 2009

Firstpage

1313

Lastpage

1316

Abstract

This paper presents a 65 nm CMOS power amplifier (PA) using a coupled transformer. The PA is based on an original structure, called stacked folded fully differential structure (SFFDS). It is applied to the UMTS W-CDMA standard. The parallel SFFDS power amplifier provides 30.5 dBm of output power with 20% of power added efficiency (PAE) at 1.95 GHz. The output compression point (OCP1) is 27.5 dBm and the PA is linear up to 24 dBm in order to meet the maximum output power required by the UMTS W-CDMA standard.

Keywords

CMOS integrated circuits; power amplifiers; power transformers; radiofrequency integrated circuits; telecommunication standards; CMOS SFFDS; CMOS power amplifier; UMTS W-CDMA standard; coupled transformer; frequency 1.95 GHz; output compression point; power added efficiency; size 65 nm; stacked folded fully differential structure; 3G mobile communication; CMOS technology; Circuit topology; High power amplifiers; Inductance; Multiaccess communication; Network topology; Power amplifiers; Power generation; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118005

Filename

5118005