Title :
An enhanced dual-path ΔΣ analog-to-digital converter
Author :
Nishida, Yoshio ; Temes, Gabor C.
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan
Abstract :
This paper presents an enhanced dual-path delta-sigma ADC. The first-order enhancement of the quantization noise shaping is achieved by employing a switched capacitor circuit technique. A test chip, fabricated in a 0.18-mum CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75- dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101-dB and the 3rd one is -94-dB when a -4.5-dB 100-kHz input signal is applied.
Keywords :
CMOS digital integrated circuits; delta-sigma modulation; CMOS process; bandwidth 1.0 MHz; bandwidth 100 kHz; bandwidth 40 MHz; dual-path DeltaSigma analog-to-digital converter; first-order enhancement; quantization noise shaping; size 0.18 mum; switched capacitor circuit technique; Adders; Analog-digital conversion; Computer science; Delay; Dynamic range; Integrated circuit noise; Multi-stage noise shaping; Noise shaping; Quantization; Signal processing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118010
