Title :
1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technology
Author :
Carrillo, Juan M. ; Montecelo, Miguel A. ; Neubauer, Harald ; Hauer, Hans ; Duque-Carrillo, J. Francisco
Author_Institution :
Dept. of Electron. & Electrom. Eng., Extremadura Univ., Badajoz, Spain
fDate :
28 Aug.-2 Sept. 2005
Abstract :
This paper deals with the design of a second-order ΣΔ modulator in 0.18-μm CMOS technology. The A/D converter structure combines a 1-bit approach along with a relatively high oversampling ratio in order to obtain a reasonable dynamic range. A circuit prototype, including the modulator itself, a current reference, and the clock signals generator, has been fabricated to operate with a 1.8-V supply. A measured SNDR equal to 87 dB is obtained for a clock frequency equal to 8 MHz, while the experimental performance of the ΣΔ modulator is maintained in a frequency range higher than 16 MHz.
Keywords :
CMOS analogue integrated circuits; clocks; integrated circuit design; sigma-delta modulation; 0.18 micron; 1.8 V; 8 MHz; A/D converter structure; CMOS technology; clock frequency; clock signal generator; current reference; oversampling ratio; second-order ΣΔ modulator; Bandwidth; CMOS technology; Clocks; Delta modulation; Frequency; Low-frequency noise; Noise reduction; Noise shaping; Prototypes; Threshold voltage;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1522944
