Integrated charge-pump phase-locked loop with SC-loop filter for capacitive microsensor readout

In this paper, simulated and measured phase noise characteristics for a charge-pump phase-locked loop (PLL) with a switched capacitor loop filter are presented. The PLL is fabricated using a 0.35 mum high-voltage CMOS technology. The PLL is designed for a reference frequency range from 3 kHz to 10 kHz, for divider value of 32, and to operate in temperature range from 40degC to +85degC and with 2.5 to 3.6 V supply. Measured results indicate that the SC-filter can be used to replace the conventional RC-filter in order to reduce area.