Title :
Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories
Author :
Haron, Nor Zaidi ; Junos, Siti Aisah Mat ; Aziz, Amir Shah Abdul
Author_Institution :
Univ. Teknikal Malaysia Melaka, Durian Tunggal
Abstract :
Memory Built-in Self Test (MBIST) or as some refer to it array built-in self-test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modeling and simulation of Microcode MBIST is presented in this paper. The design architecture is written using Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuck at fault SRAM. Five BIST algorithms are implemented i.e MATS, MATS+, MARCH X, MARCH C and March C-to test the faulty SRAM.
Keywords :
SRAM chips; built-in self test; circuit simulation; embedded systems; fault diagnosis; firmware; hardware description languages; logic design; logic testing; memory architecture; very high speed integrated circuits; VHDL; Xilinx ISE tool; embedded memory; logic verification; microcode memory built-in self test architecture; register transfer level abstraction; simulation; stuck at fault SRAM testing; very high speed integrated circuit hardware description language; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Logic arrays; Logic testing; Memory architecture; Random access memory; Very high speed integrated circuits;
Conference_Titel :
Communications and Information Technologies, 2007. ISCIT '07. International Symposium on
Conference_Location :
Sydney,. NSW
Print_ISBN :
978-1-4244-0976-1
Electronic_ISBN :
978-1-4244-0977-8
DOI :
10.1109/ISCIT.2007.4392000
