Power-aware design for high data rate free space optical receivers

A design methodology for low power front-end receiver targeting CMOS imagers for free space optical FSO communications is presented. The differential front-end is formed of two transimpedance amplifiers integrated with a Spatially Modulated Light detector SML, a Cherry-Hopper amplifier, an equalizer and a buffer stage. The circuit is implemented in 130 nm CMOS technology and is intended for incorporation in a CMOS imager for Line Of Sight LOS tracking in mobile FSO links. The front-end circuit achieves a 4GHz bandwidth, 64 dBΩ transimpedance gain and occupies an active area of 109 × 136 (μm)². It consumes 17.7 mW in total, including the differential 50 Ω output buffer, of which only 0.65 mW is consumed in the regulated cascode TIA input stage. The average input referred current noise is 17 PA/√Hz in 4 GHz bandwidth.