Title :
Low area Elliptic Curve arithmetic unit
Author :
Fournaris, Apostolos P. ; Koufopavlou, Odysseas
Author_Institution :
Comput. Eng. & Inf. Dept., Univ. of Patras, Patras, Greece
Abstract :
In this paper, a generic elliptic curve (EC) arithmetic unit with high flexibility and small chip covered area is proposed. This EC arithmetic unit is based on the one dimensional systolic architectural realization of a proposed modified multiplication - inversion algorithm that through appropriate initialization uses the algorithmic structure of inversion to also perform multiplication. The proposed architecture is realized on FPGA for GF(2163) and is compared with similar up-to-date designs. The proposed EC arithmetic unit has very small chip covered area without any serious penalty in calculation delay and since is designed on the affine coordinate plane, it offers a good side channel attack resistance base for further optimizations on this field.
Keywords :
Galois fields; digital arithmetic; field programmable gate arrays; logic design; microprocessor chips; multiplying circuits; parallel algorithms; public key cryptography; FPGA; Galois field; affine coordinate plane; low area elliptic curve arithmetic unit; multiplication-inversion algorithm; one dimensional systolic architectural realization; side channel attack resistance; small chip covered area; Algorithm design and analysis; Delay; Design optimization; Digital arithmetic; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Hardware; Information security; Power system security;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118026