A 0.8–6.3 GHz spread spectrum clock generator for SerDes transmitter clocking

The implementation of a fully integrated multi-standard low-jitter clock generator is presented. A ΣΔ fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 GHz wireline Serializer-Deserializer (SerDes) transmitting clock and spread spectrum clock generator (SSCG) for Serial AT Attachment (SATA I, II, III) characterized by a spread modulation of 5000 ppm. A multi-range voltage-controlled oscillator (VCO) is presented to handle the wide range of operation. The PLL exhibits less than 3.5 ps rms jitter at 6.3 GHz with power consumption of 7 mW from 1.2 V and 2.5 V supply. EMI reduction is 20 dB. The design has been implemented in 90 nm CMOS process and occupies an area of 0.14×0.16 mm².