DocumentCode :
2257249
Title :
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links
Author :
Abbas, Mohamed ; Cheng, Kwang-Ting ; Furukawa, Yasuo ; Komatsu, Satoshi ; Asada, Kunihiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
fYear :
2010
fDate :
8-12 March 2010
Firstpage :
1755
Lastpage :
1760
Abstract :
This paper presents a new analog ATPG (AATPG) framework that generates near-optimal test stimulus for the digitally-assisted adaptive equalizers in high-speed serial links. Based on the dynamic-signature-based testing scheme developed recently, our AATPG utilizes a Genetic Algorithm (GA) which attempts to maximize the difference between the fault-free and faulty dynamic signatures of the target fault. Our test generation framework takes into account process variations and signal noise in selecting the test stimulus, which minimizes the number of misclassified devices. The experimental results on a 5-tap feed-forward adaptive equalizer demonstrate that the GA-tests generated by our framework can effectively detect faults that are hard to detect by the hand-crafted tests.
Keywords :
adaptive equalisers; automatic test pattern generation; genetic algorithms; 5-tap feed-forward adaptive equalizer; automatic test generation framework; digitally-assisted adaptive equalizers; genetic algorithm; high-speed serial links; target fault; Adaptive equalizers; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Genetic algorithms; Signal processing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
ISSN :
1530-1591
Print_ISBN :
978-1-4244-7054-9
Type :
conf
DOI :
10.1109/DATE.2010.5457098
Filename :
5457098
Link To Document :
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