Esd Protection circuits with low triggering vlotage, low leakage current and fast turn-on

Author

Koo, Yong-Seo ; Lee, Kwang-Yeob ; Lee, Hyun-Duck ; Park, Tae-Ryoung ; Kwak, Jae-chang ; Yang, Yil-Suk

Author_Institution

Dept. of Electron. & Electr. Eng., DanKook Univ., Yongin, South Korea

fYear

2010

fDate

19-22 Dec. 2010

Firstpage

92

Lastpage

95

Abstract

ESD Protection circuits with low triggering voltage, low leakage current and fast turn-on using trigger techniques are presented in this paper. The proposed ESD protection devices are designed in 0.13um CMOS Technology. The results show that the proposed substrate Triggered NMOS using bipolar transistor has a lower trigger voltage of 5.98V and a faster turn-on time of 37ns. And the results show that the proposed gate-substrate triggered NMOS have lower trigger voltage of 5.35V and lower leakage current of 80pA.

Keywords

CMOS integrated circuits; bipolar transistor circuits; electrostatic discharge; leakage currents; low-power electronics; CMOS technology; ESD protection circuits; bipolar transistor; current 80 pA; low leakage current; low triggering voltage; time 37 ns; voltage 5.35 V; voltage 5.98 V; Bipolar transistors; CMOS integrated circuits; Electrostatic discharge; Leakage current; Logic gates; MOS devices; Substrates; ESD Protection Circuit; GGNMOS; leakage current; turn on;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics (ICM), 2010 International Conference on

Conference_Location

Cairo

Print_ISBN

978-1-61284-149-6

Type

conf

DOI

10.1109/ICM.2010.5696214

Filename

5696214