A hardware/software co-design architecture for packet classification

Packet Classification involves matching information from a packet´s header to a set of rules in a database in order to determine the manner in which the packet should be processed by network processors. The PCIU algorithm is a novel classification algorithm which improves upon previously published techniques in the literature. The main features of the PCIU algorithm are the low pre-processing time and capability of incremental rule update. Using the network processor to implement packet classification would cause saturation even when the best performing packet classification algorithm is used. In this work, we propose a hardware implementation of the PCIU algorithm. Results obtained indicate that the hardware/software co-design approach achieves 4.3x speedup in terms of preprocessing over a pure software implementation and 5.3x speedup for classification.