A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR

Author

Froehlich, Thomas ; Sharma, Vivek ; Bingesser, Markus

Author_Institution

Austriamicrosystems Switzerland AG, Rapperswil, Switzerland

fYear

2010

fDate

8-12 March 2010

Firstpage

706

Lastpage

710

Abstract

This paper presents the design of a 14 bit, 280 kS/s cyclic ADC which consumes 1.6 mW power and achieves 100 dB SFDR. The design is optimized with a half-scale residue transfer characteristic (RTC) which lowers swing and slew requirements on the opamp. Further advantages of this RTC are exploited to reduce the number and magnitude of dominant error sources, and the residual error is randomized with dithering. Capacitor scaling and optimized allocation of conversion time to each step add to power savings. The ADC fabricated in a 0.35 ??m CMOS process occupies 1.04 mm² silicon area.

Keywords

analogue-digital conversion; integrated circuit design; CMOS process; SFDR; analog-to-digital converter; capacitor scaling; conversion time; cyclic ADC; differential nonlinearity; dithering; half-scale residue transfer characteristic; integral nonlinearity; optimized allocation; residual error; Adders; Analog-digital conversion; CMOS process; Capacitors; Design optimization; Differential amplifiers; Energy consumption; Linearity; Noise reduction; Silicon; Cyclic analog-to-digital converter (ADC); differential nonlinearity (DNL); dithering; half-scale residue transfer characteristic (RTC); integral nonlinearity (INL); residue amplifier (RA);

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4244-7054-9

Type

conf

DOI

10.1109/DATE.2010.5457109

Filename

5457109