SRAM Design Techniques for Sub-nano CMOS Technology

The scaling of CMOS technology has significant impacts on SRAM cell – random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be unstable and the low power supply operation becomes hard to achieve. Besides that, the large leakage current caused by the low threshold voltage and thin gate oxide let the sub-nano SRAM design have huge static power. This makes portable electronics applications become difficult. In this talk, several design techniques used to minimize the static power consumption will be addressed and compared first. Second, in order to increase the read/write margins of SRAM cell, the VDC (Voltage Down Converter) approach will be discussed. It is founded that by using a simple VDC design, the RM (Read Margin) and WM (Write Margin) can be significantly improved and let the SRAM design be functional in the 0.7V range. The yield of the SRAM chip can also be dramatically improved. Incorporated with a resistor-less BGR (Bandgap Reference) design, this VDC can be used for static power reduction, read margin and write margin improvement, programmable voltage and voltage clamping.