CMOS image compression sensor with algorithmically-multiplying ADCs

A 128times128 CMOS image compression sensor fabricated in a 0.35 mum CMOS process is reported. It computes block-matrix and convolutional image transforms with digital kernels of up to 8times8 pixels directly on the focal plane. A pixel output is sampled only when the corresponding bit of the kernel coefficient is one. Bit-wise accumulation of adjacent pixel outputs in a column is performed by the switched-capacitor accumulator circuit. A column-parallel algorithmic multiplying ADC performs binary-weighted summation by adding the accumulator circuit outputs with cyclic residues of the same binary weight. The signal range is maintained by generating two bits per cycle. The imager performs three computations per pixel readout. Image compression experimental results at 30 fps and 8-bit output resolution are presented.