Development of a RSFQ cell library for the University of Stellenbosch

The development of an RSFQ cell library for the world´s fastest superconducting digital family is hereby presented. Cells ranging from the basic JTL to the more complex NOR gate were laid out and are ready for fabrication. In addition, cell parameters were carefully estimated and inductance extracted using special software tools. To ensure that the cells work with known parameter margins, on-chip testing of these cells are done in the laboratory. Cells ready for fabrication include the JTL, Splitter, Merger, PTL Driver and Receiver, T-flip flop, D-flip flop, OR, NOR, AND, XOR and the NOT, with the XNOR and NAND to be developed next. We discuss test steps and verification of the cells.