Title :
GoldMine: Automatic assertion generation using data mining and static analysis
Author :
Vasudevan, Shobha ; Sheridan, David ; Patel, Sanjay ; Tcheng, David ; Tuohy, Bill ; Johnson, Daniel
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Illinois at Urbana Champaign, Champaign, IL, USA
Abstract :
We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. We present results of using GoldMine for assertion generation of the RTL of a 1000-core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.
Keywords :
data mining; digital circuits; logic design; program diagnostics; 1000 core processor design; GoldMine; automatic assertion generation; data mining; register transfer level design; static analysis; Data engineering; Data mining; Formal verification; Hardware; Humans; Logic; Process design; Registers; Space technology; Testing;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5457129
