A smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4 GHz synthesizer with 1 MHz reference input was implemented in 0.35 mum CMOS process. The chip core area is 0.4 mm². Output frequency of VCO ranges from 2390 to 2600 MHz. The measured results show that the typical lock-in time is 3 mus. The phase noise is -112 dBc/Hz at 600 KHz offset from center frequency. The test chip consumes current of 22 mA that includes the consumption of the I/O buffers.