Efficient synchronizer architecture using common autocorrelator for DVB-S2

This paper presents an efficient synchronizer architecture using the common autocorrelator for digital video broadcasting via satellite, second generation (DVB-S2). To achieve the satisfactory performance under worst channel condition and the efficient H/W resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&Strade SFU broadcast test equipment.