A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΣΔ ADC

This paper presents a reconfigurable high-pass (HP) time-interleaved (TI) delta-sigma (SigmaDelta) analog-to-digital converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the SigmaDelta modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwidth-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm^{2 .}