A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices

Author

Cakici, Tamer ; Bansal, Aditya ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2003

fDate

29 Sept.-2 Oct. 2003

Firstpage

21

Lastpage

22

Abstract

In this paper, we present a novel low power 4 Transistor Schmitt Trigger (4T-ST) for asymmetric double gate fully depleted silicon-on-insulator (DGFDSOI) devices. The new ST is compared to conventional 6 Transistor Schmitt Trigger (6T-ST) scheme realized with symmetric (SymD) and asymmetric devices (AsymDs). Power dissipation and gate area are reduced by switching from conventional scheme to proposed scheme at iso noise-immunity (isoNT) and comparable delay.

Keywords

MOS integrated circuits; MOSFET; delays; elemental semiconductors; low-power electronics; semiconductor device models; semiconductor device noise; silicon-on-insulator; trigger circuits; SOI devices; Si-SiO₂; asymmetric double gate silicon-on-insulator device; noise-immunity; power dissipation; power four transistor Schmitt trigger; symmetric devices; Delay effects; MOS integrated circuits; MOSFETs; Semiconductor device modeling; Semiconductor device noise; Silicon on insulator technology; Trigger circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2003. IEEE International

ISSN

1078-621X

Print_ISBN

0-7803-7815-6

Type

conf

DOI

10.1109/SOI.2003.1242882

Filename

1242882