A 2.0-V folding circuit using current limiting amplifier for ADC

Author

Koike, Takeshi ; Hyogo, Akira ; Sekine, Keitaro

Author_Institution

Dept. of Electr. Eng., Tokyo Univ. of Sci., Japan

Volume

2

fYear

2005

fDate

28 Aug.-2 Sept. 2005

Abstract

This paper presents a low voltage folding circuit for folding and interpolating ADCs. In general, reducing the supply voltage of the conventional folding circuit with source coupled pairs prevents it from working because the conventional circuit has large output voltage range, and it is difficult to decrease the reference voltages. This is because decreasing reference voltages cause increasing zero-crossing error and decreasing peak output current. The proposed circuit using current limiting amplifier realizes small zero-crossing error and a supply voltage of 2.0V. The operation has been confirmed by simulation using a 0.35μm CMOS technology.

Keywords

CMOS analogue integrated circuits; amplifiers; analogue-digital conversion; current limiters; integrated circuit design; low-power electronics; reference circuits; 0.35 micron; 2.0 V; ADC interpolation; CMOS technology; current limiting amplifiers; low voltage folding circuit; peak output current; reference voltage; supply voltage reduction; zero-crossing error; Analog circuits; CMOS digital integrated circuits; CMOS technology; Circuit simulation; Coupling circuits; Current limiters; Digital circuits; Low voltage; Signal generators; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on

Print_ISBN

0-7803-9066-0

Type

conf

DOI

10.1109/ECCTD.2005.1522993

Filename

1522993