Title :
A high-speed sense-amplifier based flip-flop
Author :
DeCaro, D. ; Napoli, E. ; Petra, N. ; Strollo, A.G.M.
Author_Institution :
Dept. of Electron. & Telecom. Eng., Univ. of Naples "Federico II", Italy
fDate :
28 Aug.-2 Sept. 2005
Abstract :
The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C2MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25μm technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
Keywords :
CMOS logic circuits; amplifiers; flip-flops; high-speed integrated circuits; 0.25 micron; N-C2MOS approach; NAND based SR latch; clock-to-output delay; high speed sense amplifiers; power dissipation reduction; sense amplifier based flip flop; Circuits; Clocks; Flip-flops; Latches; Pipelines; Power dissipation; Propagation delay; Sampling methods; Strontium; Switches;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1523002
